中国科学院机构知识库网格系统: 检索

An Agent-Based Traffic Recommendation System: Revisiting and Revising Urban Traffic Management Strategies 期刊论文 OAI收割
IEEE TRANSACTIONS ON SYSTEMS MAN CYBERNETICS-SYSTEMS, 2022, 页码: 13
作者: Jin, Junchen; Rong, Dingding; Pang, Yuqi; Ye, Peijun; Ji, Qingyuan

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收藏 | 浏览/下载：47/0 | 提交时间：2022/07/25

Switches Control systems Timing Task analysis Behavioral sciences Analytical models Research and development Agent-based recommendation system deep recommendation human-in-the-loop operation on-demand traffic management strategies

The Central Control System for KTX 期刊论文 OAI收割
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2018, 卷号: 65, 期号: 8, 页码: 2357-2361
作者: Zhang, Z.; Xiao, B.

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收藏 | 浏览/下载：30/0 | 提交时间：2019/11/11

Central control system (CCS) gas injection network reversed field pinch (RFP) safety and interlock timing

Implementation of an FPGA controller for correction power supplies in heavy ion synchrotron 期刊论文 OAI收割
NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT, 2015, 卷号: 777, 页码: 167-171
作者: Li, Peng; Yuan, Youjin; Zhou, Zhongzu; Wu, Fengjun; Yan, Huaihai

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收藏 | 浏览/下载：45/0 | 提交时间：2018/07/05

Cancer Therapy Orbit Correction Timing System Synchronization Control Waveform Control

Upgrade of a kicker control system for the HIRFL 期刊论文 OAI收割
NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT, 2014, 卷号: 738, 页码: 50-53
作者: Wang, Yan-Yu; Zhou, Wen-Xiong; Luo, Jin-Fu; Zhou, De-Tai; Zhang, Jian-Chuan

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收藏 | 浏览/下载：23/0 | 提交时间：2018/07/05

Hirfl Kicker Control System Timing Fpga

The status and improvement of the HIRFL-CSR operation software 期刊论文 OAI收割
NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT, 2013, 卷号: 697, 页码: 17-22
作者: Xia, JW; Li, P (reprint author), Chinese Acad Sci, IMP, 509 Nan Chang Rd, Lanzhou 730000, Peoples R China.; Yuan, YJ; Li, P; Chai, WP

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收藏 | 浏览/下载：29/0 | 提交时间：2017/04/05

HIRFL-CSR Accelerator control Timing system Operation software

Design of driving circuit for binocular CCD image system (EI CONFERENCE) 会议论文 OAI收割
5th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optoelectronic Materials and Devices for Detector, Imager, Display, and Energy Conversion Technology, April 26, 2010 - April 29, 2010, Dalian, China
作者: Zhang X.; Zhang X.; Zhang X.

收藏 | 浏览/下载：53/0 | 提交时间：2013/03/25

The paper designs a driving circuit of high sensitive wide dynamic and high signal-to-noise ratio for binocular CCD imaging system which adopts a Dalsa-made high resolution full-frame 33-mega pixels area CCD FTF5066M. Inner structure and driving timing of the FTF5066M sensor are presented. Field Programmable Gate Array (FPGA) is used as the main device to accomplish the timing design of the circuits and power driver control of the two sensors. By using the Correlated Double Sampling (CDS) technique the video noise is reduced and the SNR of the system is increased. A 12- bit A/D converter is used to improve the image quality. The output rate of the imaging system designed with integrated chip can reach to 1.3 frames per second through bi-channel. For its good performance low power consumption and small volume the driving system can be applied to aeronautics and astronautics field. With a further improvement a maximum data output rate of 2.7 frames per second can be reached through all the eight channels of the two CCDs. 2010 Copyright SPIE - The International Society for Optical Engineering.

The design of acquisition circuit for grating digital signal based on FPGA (EI CONFERENCE) 会议论文 OAI收割
2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010, August 20, 2010 - August 22, 2010, Chengdu, China
作者: Wang W.-G.

收藏 | 浏览/下载：48/0 | 提交时间：2013/03/25

In order to resolve the poor suppression capability of noise and fitter interference existing in grating encoder high-rate subdivision and the poor accuracy of kam-to counting circuit the results show that the design method will help improve the controlled object of measurement precision and control accuracy. 2010 IEEE. we design a circuit based on FPGA to realize multiplier kam and filter for the output of two-way orthogonal signal generated by Incremental Optical Encoder. The system is mainly divided into three modules such as filtering multiplier kam-to and counting. The main function of filter circuit is to eliminate the jitter and noise interference existing in the quadrate encoder signals. Kam-to multiplier circuit can accurately judge the full cycle and half-cycle of incremental encoder at the same time can make fourfold multiplier. Counting circuit can use IP cores owned by Quartus II which is not restricted on the median. At last timing simulation based on Modelsim carried on the three modules

Driving and image enhancement for CCD sensing image system (EI CONFERENCE) 会议论文 OAI收割
2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010, July 9, 2010 - July 11, 2010, Chengdu, China
Zhang M.; Ren J.

收藏 | 浏览/下载：46/0 | 提交时间：2013/03/25

The paper designs a driving circuit of high sensitive wide dynamic for CCD sensing imaging system which adopts a Dalsa-made high resolution full-frame 33-mega pixels area CCD FTF5066M. Field Programmable Gate Array (FPGA) is used as the main device to accomplish the timing design of the circuits and power driver control of the sensor. By using the Correlated Double Sampling (CDS) technique the video noise is reduced and the SNR of the system is increased. The output rate of the imaging system designed with integrated chip can reach to 1.3 frames per second through bi-channel output. We use the histogram specification to adjust the brightness of the captured image. And then use the median filtering to suppress the noise. The traditional gray mean gradient (GMG) and the objective evaluation method based on Human Visual System (HVS) used to verify the effect of image enhancement. 2010 IEEE.

The design of high-speed optical fiber communication system based on PCI bus (EI CONFERENCE) 会议论文 OAI收割
2010 2nd IEEE International Conference on Advanced Management Science, ICAMS 2010, July 9, 2010 - July 11, 2010, Chengdu, China
作者: Zhang L.-G.; Zhang L.-G.; He X.

收藏 | 浏览/下载：64/0 | 提交时间：2013/03/25

In order to increase the transmission distance and reduce noise effectively a communication system with the optical fiber interface is developed in this paper. In the system the PCI bus is adopted as the connection bus between the underlying optical fiber transceiver module circuitry and host computer using the WDM driver. The FPGA is the core logic of the whole system responsible for data transmission and timing logic control. The module structure and the design method of the PCI bus the principle and the design of optical interface module and the bottom-driven development are described in this paper. The experiment results show that the system has basically meet requirement targets. It can achieve the maximum transfer rate of 40MBps when running in the DMA mode. With long transmission distance strong antiinterference and high scalability this system has stable and reliable performance. 2010 IEEE.

Design and implementation of a high speed CMOS imaging system (EI CONFERENCE) 会议论文 OAI收割
2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010, August 20, 2010 - August 22, 2010, Chengdu, China
作者: He X.

收藏 | 浏览/下载：38/0 | 提交时间：2013/03/25

In order to meet the needs of measurement of highspeed target the timing sequence of LUPA300 an array CMOS image sensor of CYPRESS is analyzed. The driving timing and control software is designed for the array CMOS sensor. High speed CMOS imaging system whose hardware platform is FPGA is emphasized. Real-time non-uniformity correction for CMOS sensor is implemented in the output stage. The experimental result shows that the system could control the CMOS sensor flexibly. The image is clear and stable. The maximum resolution of the image is 640H480V pixels and the system can operate up to 250 frames per second in full resolution. 2010 IEEE.