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	The Benefits of Receiver Clock Modelling in Satellite Timing 期刊论文 OAI收割 SENSORS, 2021, 卷号: 21, 期号: 2, 页码: 15 作者: Qin, Weijin; Wang, Xiao; Su, Hang; Zhang, Zhe; Li, Xiao \| 收藏 \| 浏览/下载：40/0 \| 提交时间：2021/11/29 timing stochastic clock model PPP kinematic scheme static scheme
	Distributed Self-Clock: A Suitable Architecture for SFQ Circuits 期刊论文 OAI收割 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2020, 卷号: 30, 期号: 7, 页码: 7 作者: Yang, Jia-Hong; Tang, Guang-Ming; Zheng, Xiang-Yu; Ye, Xiao-Chun; Fan, Dong-Rui \| 收藏 \| 浏览/下载：45/0 \| 提交时间：2020/12/10 Integrated circuit microprocessors single flux quantum (SFQ) timing scheme
	Design of high speed and parallel compression system used in the big area CCD of high frame frequency (EI CONFERENCE) 会议论文 OAI收割 2011 International Conference on Precision Engineering and Non-Traditional Machining, PENTM 2011, December 9, 2011 - December 11, 2011, Xi'an, China 作者: Li G.-N.; Jin L.-X.; Zhang R.-F.; Wang W.-H.; Li G.-N. 收藏 \| 浏览/下载：55/0 \| 提交时间：2013/03/25 According to the area CCD camera of characteristics such as high resolution capacity and high frame frequency this paper puts forward a high speed and parallel image compression system of high integration degree. Firstly according to the work principle of the area CCD FPGA is adopted to realize the timing driving and multichannel and parallel analog signal handling to raise the export frame frequency of the area CCD. Secondly with an image compression scheme based on FPGA embedded processor MicroBlaze and ADV212 compression chip real time image compression and the high speed area CCD are realized. Finally by detecting the analog signal of the area CCD output the real time compression of the big area CCD image is carried out in different compression ratios and the compression performance is analyzed. Experiment result shows that this scheme can realize real time image compression with the biggest data rate of 520Mbps. When compression bit ratio is 0.15 the signal-to-noise ratio of peak value can reach 36 dB. Image collection and image compression are integrated which reduces the data transmission between them and improves systematic integration degree.
	An 8-channel, area-efficient, low-power audio sampling rate converter (EI CONFERENCE) 会议论文 OAI收割 9th International Conference on Electronic Measurement and Instruments, ICEMI 2009, August 16, 2009 - August 19, 2009, Beijing, China 作者: Liu Y.; Liu Y.; Liu Y.; Wang D. 收藏 \| 浏览/下载：33/0 \| 提交时间：2013/03/25 A novel 8-channle third area-efficient next a new Timing Division Multiplexer (TMD) scheme lowers clock working rate to minimum in order to save power a novel memory addressing scheme reduces 20% data memory at least. Experiments show proposed methods could not only saved hardware resources but also reduce power consumption low-power audio sampling rate converter is proposed in this paper so it is very suitable for consumer electronics. 2009 IEEE. conversion ratio is 2:1 and 4:1. Filter design and implementation are the key points for the converter. First excluded data and coefficients memories adopting multiplier-free Arithmetic Unit (AU) and rounding methods allows its realization in a cell area of only 0.038mm 2 in 0.18 m technology
	A multi-channel, area-efficient, audio sampling rate interpolator (EI CONFERENCE) 会议论文 OAI收割 2009 8th IEEE International Conference on ASIC, ASICON 2009, October 20, 2009 - October 23, 2009, Changsha, China 作者: Wang D. 收藏 \| 浏览/下载：34/0 \| 提交时间：2013/03/25 The area and power consumption of sampled rate converter are governed largely by associated digital interpolationfilters. This paper presents a novel multi-channel area-efficient audio sampling rate interpolator whose conversion ratio is 1:2 and 1:4. Several architectural and implementation features reduces the complexity of the filter and allow its realization in a die area of 0.032mm2 in 0.18 m technology meanwhile timing multiplexer scheme reduces clock frequency to minimum. Experiments show proposed methods could not only saved hardware resources but also reduce power consumption so it is very suitable for consumer electronics. 2009 IEEE.
	Design and DSP implementation of star image acquisition and Star point fast acquiring tracking (EI CONFERENCE) 会议论文 OAI收割 2nd International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optical Test and Measurement Technology and Equipment, November 2, 2005 - November 5, 2005, Zian, China 作者: Wang X.; Wang X.; Wang X. 收藏 \| 浏览/下载：31/0 \| 提交时间：2013/03/25 Star sensor is a special high accuracy photoelectric sensor. Attitude acquisition time is an important function index of star sensor. In this paper the design target is to acquire 10 samples per second dynamic performance. On the basis of analyzing CCD signals timing and star image processing a new design and a special parallel architecture for improving star image processing are presented in this paper. In the design the operation moving the data in expanded windows including the star to the on-chip memory of DSP is arranged in the invalid period of CCD frame signal. During the CCD saving the star image to memory DSP processes the data in the on-chip memory. This parallelism greatly improves the efficiency of processing. The scheme proposed here results in enormous savings of memory normally required. In the scheme DSP HOLD mode and CPLD technology are used to make a shared memory between CCD and DSP. The efficiency of processing is discussed in numerical tests. Only in 3.5ms is acquired the five lightest stars in the star acquisition stage. In 43us the data in five expanded windows including stars are moved into the internal memory of DSP and in 1.6ms five star coordinates are achieved in the star tracking stage.
	An image identification system of seal with fingerprint based on CMOS image sensor (EI CONFERENCE) 会议论文 OAI收割 ICO20: Optical Information Processing, August 21, 2005 - August 26, 2005, Changchun, China 作者: Xue X.-C. 收藏 \| 浏览/下载：21/0 \| 提交时间：2013/03/25 CMOS image sensors now become increasingly competitive with respect to their CCD counterparts while adding advantages such as no blooming simpler driving requirements and the potential of on-chip integration of sensor analog signal conditioning circuits A/D converter and digital processing functions. Furthermore CMOS sensors are the best choices for low-cost imaging systems. An image identification system based on CMOS image sensor is used to identify the seal images that include fingerprint and then determine whether the seal is fake or not. The system consists of a color CMOS image sensor (OV2610) a buffer memory a CPLD a MCU (P89C61X2) a USB2.0 interface chip (ISP1581) and a personal computer. The CPLD implement the logic and timing of the system. The MCU and the USB2.0 interface chip deal with the communications between the images acquisition system and PC. Thus PC can send some parameters and commands to the images acquisition system and also read image data from it. The identification of the images of seal is processed by the PC. The structure and scheme of the system are discussed in detail in this paper. Several test images of seal taken by the system are also provided in the paper.