中国科学院机构知识库网格
Chinese Academy of Sciences Institutional Repositories Grid
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CAS IR Grid
机构
计算技术研究所 [3]
长春光学精密机械与物... [1]
采集方式
OAI收割 [4]
内容类型
期刊论文 [3]
会议论文 [1]
发表日期
2016 [1]
2012 [1]
2007 [2]
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VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache
期刊论文
OAI收割
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 3, 页码: 858-870
作者:
Wang, Ying
;
Han, Yinhe
;
Li, Huawei
;
Li, Xiaowei
  |  
收藏
  |  
浏览/下载:31/0
  |  
提交时间:2019/12/13
Cache design
fault tolerant
multi-V-dd
near-threshold voltage (NTV)
nonuniform cache access (NUCA)
Research of software re-injection technology for aerospace camera controller in-orbit (EI CONFERENCE)
会议论文
OAI收割
2012 9th IEEE International Conference on Mechatronics and Automation, ICMA 2012, August 5, 2012 - August 8, 2012, Chengdu, China
Xu W.
收藏
  |  
浏览/下载:20/0
  |  
提交时间:2013/03/25
For the factors of increased of tasks
enhancements of functions and improvement of integrity and complexity in aerospace camera
application system has raised high and long-term in-orbit autonomy and reliability requirements on camera controller. Based on an actual project application background
this paper has put forward a design method of new high reliability aerospace camera controller in-orbit software reinjection instruction sequence which use TSC695F as kernel CPU and process flow of bootstrap receive
cache
checkout and storage update data. Finally
combined with specific test module for camera controller software re-injection
the validity of the software re-injection method raised here has been verified. Still here gives out reference codes of update data package which generated by the ground. 2012 IEEE.
Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology
期刊论文
OAI收割
Journal of Computer Science and Technology, 2007, 卷号: 22, 期号: 1, 页码: 1
作者:
Elio Guidetti
;
Wei-Wu Hu(胡伟武)
;
Ji-Ye Zhao(赵继业)
;
Shi-Qiang Zhong(钟石强)
;
Xu Yang(杨旭)
  |  
收藏
  |  
浏览/下载:11/0
  |  
提交时间:2010/11/02
General-purpose Processor
Superscalar Pipeline
Out-of-order Execution
Non-blocking Cache
Physical Design
Synthesis Flow
Bit-sliced Placement
Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology
期刊论文
OAI收割
JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2007, 卷号: 22, 期号: 1, 页码: 1-14
作者:
Hu, Wei-Wu
;
Zhao, Ji-Ye
;
Zhong, Shi-Qiang
;
Yang, Xu
;
Guidetti, Elio
  |  
收藏
  |  
浏览/下载:16/0
  |  
提交时间:2019/12/16
general-purpose processor
superscalar pipeline
out-of-order execution
non-blocking cache
physical design
synthesis flow
bit-sliced placement
crafted cell
performance evaluation