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	SRAM型FPGA在辐照环境下的容错技术研究学位论文 OAI收割中国科学院大学光电技术研究所: 中国科学院大学, 2019 作者: 薛晓良 \| 收藏 \| 浏览/下载：37/0 \| 提交时间：2019/06/26 Sram型fpga，virtex-5，配置ram，icap，seu，必要位，帧结构
	自定义FPGA测试系统的设计与应用期刊论文 OAI收割计算机测量与控制, 2012, 期号: 09, 页码: 2363-2365 作者: 宁永慧; 刘辉; 马天波收藏 \| 浏览/下载：16/0 \| 提交时间：2013/03/11 Virtex5测试系统软件测试并行处理
	雷达目标跟踪的粒子滤波算法研究及实现学位论文 OAI收割硕士: 中国科学院研究生院, 2010 叶斌丽收藏 \| 浏览/下载：46/0 \| 提交时间：2014/05/04 跟踪雷达非合作目标跟踪粒子滤波重采样 FPGA Virtex-5
	Embedded system of image storage based on Fiber Channel (EI CONFERENCE) 会议论文 OAI收割 Quantum Optics, Optical Data Storage, and Advanced Microlithography, November 12, 2007 - November 14, 2007, Beijing, China 作者: Wang H.; Wang H.; Wang H.; Wang H.; Chen X. 收藏 \| 浏览/下载：19/0 \| 提交时间：2013/03/25 In domains of aerospace aviation aiming and optic measure etc. the embedded system of imaging processing and recording is absolutely necessary which has small volume high processing speed and high resolution. But the embedded storage technology becomes system bottleneck because of developing slowly. It is used to use RAID to promote storage speed but it is unsuitable for the embedded system because of its big volume. Fiber channel (FC) technology offers a new method to develop the high-speed portable storage system. In order to make storage subsystem meet the needs of high storage rate make use of powerful Virtex-4 FPGA and high speed fiber channel advance a project of embedded system of digital image storage based on Xilinx Fiber Channel Arbitrated Loop LogiCORE. This project utilizes Virtex4 RocketIO MGT transceivers to transmit the data serially and connects many Fiber Channel hard drivers by using of Arbitrated Loop optionally. It can achieve 400MBps storage rate breaks through the bottleneck of PCI interface and has excellences of high-speed real-time portable and massive capacity.
	基于FPGA的动态可重构系统实现期刊论文 OAI收割电子器件, 2007, 卷号: 30, 期号: 2, 页码: 645-650 周盛雨; 孙辉先; 陈晓敏; 安军社; 张健收藏 \| 浏览/下载：43/0 \| 提交时间：2014/04/30 FPGA 动态重构部分重构 Virtex SelectMAP
	实现FPGA回读功能的可重构系统设计期刊论文 OAI收割计算机工程, 2007, 卷号: 33, 期号: 12, 页码: 270-271,274 周盛雨; 孙辉先; 陈晓敏; 安军社; 张健收藏 \| 浏览/下载：23/0 \| 提交时间：2014/04/30 可重构 FPGA SelectMAP CPLD 回读 Virtex
	基于BIST测试Xilinx Virtex-Ⅱ系列FPGA 期刊论文 OAI收割仪器仪表学报, 2007, 卷号: 28, 期号: S, 页码: 837-840 作者: 杨志家; 王宏; 刘肄倬 \| 收藏 \| 浏览/下载：20/0 \| 提交时间：2010/11/29 Virtex-ⅱ Fpga Bist测试互连技术可测性设计内建自测试
	Design and implementation of high-speed digital CMOS camera driving control timing and data interface (EI CONFERENCE) 会议论文 OAI收割 Sixth International Symposium on Instrumentation and Control Technology: Sensors, Automatic Measurement, Control and Computer Simulation, October 13, 2006 - October 15, 2006, Beijing, China 作者: Wang Y.; Wang Y.; Wang Y.; Sun H.; Sun H. 收藏 \| 浏览/下载：37/0 \| 提交时间：2013/03/25 High-speed digital cameras are progressing rapidly with the development of CMOS image sensor in these few years. In order to develop a high-speed CMOS industrial digital camera the CMOS image sensor MI-MV13 is used. The sensor drive pulse and control timing based on Xilinx Virtex-II Pro FPGA is designed. A novel format of digital image transporting based on Camera Link data port is defined in this paper. It is implemented 1280 (H) 1024 (V) SXGA resolution digital image transported at a high frame rate of 300 fps (frames-per-second) with 5 Pixels 10 bit compatible Camera Link Medium Configuration. In addition these functions that adjustments of exposure beginning time integral time AOI (Area of Interest) output and so on are realized in a FPGA chip. All of the function modules are embedded in a SOPC (System on a Programmable Chip) and further functions can be easily added to the chip at the second time development. Experimental results show that the design of driving control timing and data interface in FPGA is suitable for high-frame rate low power intelligent and miniaturization digital video camera.
	一种快速流水线的动态阈值算法期刊论文 OAI收割红外, 2005, 卷号: 26, 期号: 10, 页码: 22-24 作者: 彭鼎祥 \| 收藏 \| 浏览/下载：23/0 \| 提交时间：2011/11/14 目标分割动态自适应阈值 Virtex Ii Pro平台fpga　流水线