机构

• 计算技术研究所 [4]
• 长春光学精密机械与物... [1]
• 中国科学院大学 [1]

采集方式

• OAI收割 [5]
• iSwitch采集 [1]

内容类型

• 期刊论文 [5]
• 会议论文 [1]

发表日期

• 2014 [1]
• 2009 [1]
• 2006 [3]
• 2005 [1]

学科主题

筛选

浏览/检索结果: 共6条，第1-6条 帮助 条数/页： 5101520253035404550556065707580859095100 排序方式： 请选择题名升序题名降序提交时间升序提交时间降序作者升序作者降序发表日期升序发表日期降序 Auxiliary stream for optimizing memory access of video decoders 期刊论文  OAI收割 SCIENCE CHINA-INFORMATION SCIENCES, 2014, 卷号: 57, 期号: 1 作者:  Liu Shaoli;  Li Ling;  Chen Yunji;  Hu Weiwu   |  收藏  |  浏览/下载：15/0  |  提交时间：2023/12/04 MOTION COMPENSATION  HIGH-PERFORMANCE  HDTV DECODER  ARCHITECTURE  STANDARDS  CHIP  video decoding  video coding  memory access  motion compensation  auxiliary information   Storage and compression design of high speed CCD (EI CONFERENCE) 会议论文  OAI收割 4th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optical Test and Measurement Technology and Equipment, November 19, 2008 - November 21, 2008, Chengdu, China Cai X.; Zhai L. P. 收藏  |  浏览/下载：57/0  |  提交时间：2013/03/25 In current field of CCD measurement  large area and high resolution CCD is used to obtain big measurement image  so that  speed and capacity of CCD requires high performance of later storage and process system. The paper discusses how to use SCSI hard disk to construct storage system and use DSPs and FPGA to realize image compression. As for storage subsystem  Because CCD is divided into multiplex output  SCSI array is used in RAID0 way. The storage system is composed of high speed buffer  DMA controller  control MCU  SCSI protocol controller and SCSI hard disk. As for compression subsystem  according to requirement of communication and monitor system  the output is fixed resolution image and analog PAL signal. The compression means is JPEG2000 standard  in which  9/7 wavelets in lifting format is used. 2 DSPs and FPGA are used to compose parallel compression system. The system is composed of FPGA pre-processing module  DSP compression module  video decoder module  data buffer module and communication module. Firstly  discrete wavelet transform and quantization is realized in FPGA. Secondly  entropy coding and stream adaption is realized in DSPs. Last  analog PAL signal is output by Video decoder. Data buffer is realized in synchronous dual-port RAM and state of subsystem is transfer to controller. Through subjective and objective evaluation  the storage and compression system satisfies the requirement of system. 2009 SPIE.   An avs hdtv video decoder architecture employing efficient hw/sw partitioning 期刊论文  iSwitch采集 Ieee transactions on consumer electronics, 2006, 卷号: 52, 期号: 4, 页码: 1447-1453 作者:  Jia, Huizhu;  Zhang, Peng;  Xie, Don;  Gao, Wen 收藏  |  浏览/下载：27/0  |  提交时间：2019/05/10 Avs  Hw/sw partition  Video decoder  Hdtv   An AVS HDTV video decoder architecture employing efficient HW/SW partitioning 期刊论文  OAI收割 IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 2006, 卷号: 52, 期号: 4, 页码: 1447-1453 作者:  Jia, Huizhu;  Zhang, Peng;  Xie, Don;  Gao, Wen   |  收藏  |  浏览/下载：23/0  |  提交时间：2019/12/16 AVS  HW/SW partition  video decoder  HDTV   An efficient VLSI architecture of VLD for AVS HDTV decoder 期刊论文  OAI收割 IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 2006, 卷号: 52, 期号: 2, 页码: 696-701 作者:  Sheng, Bin;  Gao, Wen;  Xie, Don;  Wu, Di   |  收藏  |  浏览/下载：21/0  |  提交时间：2019/12/16 Variable Length Code Decoder  AVS  video decoder  VLSI   Rate-distortion analysis for H.264/AVC video coding and its application to rate control 期刊论文  OAI收割 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2005, 卷号: 15, 期号: 12, 页码: 1533-1544 作者:  Ma, SW;  Gao, W;  Lu, Y   |  收藏  |  浏览/下载：20/0  |  提交时间：2019/12/16 H.264/AVC  hypothetical reference decoder (HRD)  rate control  rate-distortion optimization (RDO)  video coding