中国科学院机构知识库网格系统: 检索

浏览/检索结果: 共4条，第1-4条

帮助

条数/页：排序方式：
	中国沿海港区陆路集疏运能力空间结构与类型分异期刊论文 OAI收割地理与地理信息科学, 2020, 卷号: 36, 期号: 1, 页码: 107 作者: 李绪茂; 王成金 \| 收藏 \| 浏览/下载：18/0 \| 提交时间：2021/03/16 port port area collection and distribution capacity type differentiation 港口港区集疏运能力类型分异
	中国沿海港区陆路集疏运能力空间结构与类型分异期刊论文 OAI收割地理与地理信息科学, 2020, 卷号: 36, 期号: 1, 页码: 107 作者: 李绪茂; 王成金 \| 收藏 \| 浏览/下载：17/0 \| 提交时间：2021/03/16 port port area collection and distribution capacity type differentiation 港口港区集疏运能力类型分异
	Storage and compression design of high speed CCD (EI CONFERENCE) 会议论文 OAI收割 4th International Symposium on Advanced Optical Manufacturing and Testing Technologies: Optical Test and Measurement Technology and Equipment, November 19, 2008 - November 21, 2008, Chengdu, China Cai X.; Zhai L. P. 收藏 \| 浏览/下载：58/0 \| 提交时间：2013/03/25 In current field of CCD measurement large area and high resolution CCD is used to obtain big measurement image so that speed and capacity of CCD requires high performance of later storage and process system. The paper discusses how to use SCSI hard disk to construct storage system and use DSPs and FPGA to realize image compression. As for storage subsystem Because CCD is divided into multiplex output SCSI array is used in RAID0 way. The storage system is composed of high speed buffer DMA controller control MCU SCSI protocol controller and SCSI hard disk. As for compression subsystem according to requirement of communication and monitor system the output is fixed resolution image and analog PAL signal. The compression means is JPEG2000 standard in which 9/7 wavelets in lifting format is used. 2 DSPs and FPGA are used to compose parallel compression system. The system is composed of FPGA pre-processing module DSP compression module video decoder module data buffer module and communication module. Firstly discrete wavelet transform and quantization is realized in FPGA. Secondly entropy coding and stream adaption is realized in DSPs. Last analog PAL signal is output by Video decoder. Data buffer is realized in synchronous dual-port RAM and state of subsystem is transfer to controller. Through subjective and objective evaluation the storage and compression system satisfies the requirement of system. 2009 SPIE.
	Design and implementation of high-speed digital CMOS camera driving control timing and data interface (EI CONFERENCE) 会议论文 OAI收割 Sixth International Symposium on Instrumentation and Control Technology: Sensors, Automatic Measurement, Control and Computer Simulation, October 13, 2006 - October 15, 2006, Beijing, China 作者: Wang Y.; Wang Y.; Wang Y.; Sun H.; Sun H. 收藏 \| 浏览/下载：39/0 \| 提交时间：2013/03/25 High-speed digital cameras are progressing rapidly with the development of CMOS image sensor in these few years. In order to develop a high-speed CMOS industrial digital camera the CMOS image sensor MI-MV13 is used. The sensor drive pulse and control timing based on Xilinx Virtex-II Pro FPGA is designed. A novel format of digital image transporting based on Camera Link data port is defined in this paper. It is implemented 1280 (H) 1024 (V) SXGA resolution digital image transported at a high frame rate of 300 fps (frames-per-second) with 5 Pixels 10 bit compatible Camera Link Medium Configuration. In addition these functions that adjustments of exposure beginning time integral time AOI (Area of Interest) output and so on are realized in a FPGA chip. All of the function modules are embedded in a SOPC (System on a Programmable Chip) and further functions can be easily added to the chip at the second time development. Experimental results show that the design of driving control timing and data interface in FPGA is suitable for high-frame rate low power intelligent and miniaturization digital video camera.